1. Field of Invention
The present invention relates to a memory device and a fabrication method thereof, and particularly to a non-volatile memory (NVM) and a fabrication method thereof.
2. Description of the Related Art
Non-volatile memories (NVMs) can be written, erased and retain data after power is off. In addition, NVMs have other advantages such as small size, fast access speed and low electricity consumption. Since data is erased “block by block”, the operation speed of NVMs is fast. Therefore, the NVM has become a memory device widely applied in PC and various electronic devices.
A NVM comprises a plurality of memory cells (MCs) arranged in an array. Wherein, each MC is formed by a tunneling layer, a charge storage layer, a charge barrier layer and a control gate layer stacked in sequence. Besides, at both sides of the gate in the substrate are disposed with two doping regions serving as a source region and a drain region, respectively.
As data is written into the memory, a bias voltage is applied to the control gate layer, the source region and the drain region to inject electrons into the control gate layer. When data is read from the memory, an operation voltage is applied to the control gate layer. The charging status of the charge storage layer affects the switching on/off status of the channel underneath, which serves to determine the “0” or “1” of the data value. While data in the memory is erased, the relative voltage levels of the substrate, the source region, the drain region or the control gate layer are increased, so that the electrons in the charge storage layer penetrate through the tunneling layer into the substrate by a tunneling effect. The erasing method is usually termed as “substrate erase”.
Note that although the IC develops towards higher integrity and minimal size, yet along with larger application software today, the required memory capacity is accordingly bigger. To adapt such challenge where a memory is required to have a smaller size with a bigger capacity, the conventional memory cell (MC) structure and the fabrication method thereof must be modified and updated. In fact, it has been an important topic in the deep sub-micron (DSM) technology to enhance the level of integration while keeping the original memory capacity in a limited space.